Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic may be programmed to implement a user design by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
The functionality of a user design implemented by a PLD is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells), in non-volatile memory (e.g., FLASH memory), or in any other type of memory cell. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
The development of a user design to be implemented in a PLD may include simulation of the operation of the user design to verify the proper operation of the user design. Verification of the user design may continue with a prototype implementation of the user design in a PLD. Verification of the user design may require access to the state of the user design that is stored in the user registers. Simulation may provide ready access to the state of the user design stored in the user registers, while access to the user registers may be difficult and time consuming for the prototype implementation of the user design in the PLD. However, verification during simulation may be limited by the speed of simulation, which may be much slower than the speed of operation of the prototype implementation of the user design. Thus, access to registers of a user design implemented in a PLD may be required during verification, especially verification that the user design behaves properly during extended operation.
Often, a designer requiring access to registers of the design develops custom logic for accessing the registers, and developing the custom logic may be time consuming and expensive. The custom logic may consume programmable logic and interconnect resources, such that the resources required to implement this custom logic and the user design may exceed the available resources of the PLD.
The present invention may address one or more of the above issues.